1. Field of the Invention
The present invention relates to touch control technology and more particularly, to an ESD protection circuit assembly for use in a CMOS manufacturing process, in which an electrostatic discharge clamp circuit having a series of low voltage P-type structures connected thereto is electrically connected to the I/O circuit to double the withstand voltage so that a high ESD tolerance can be provided with a small circuit layout area.
2. Description of the Related Art
Today's semiconductor process technology continues to evolve and progress. The integrated circuits fabricated using CMOS technology have been designed to meet the needs of small-size and high-density. Nowadays, the CMOS manufacturing process has been changing from the original sub-micron to deep sub-micron era. As most of the integrated circuits contain MOSFET, various structural and processing requirements such as thinner gate oxide, shorter channel length, shallower source/drain junction and lower doping concentration will greatly reduce the ESD tolerance of the device itself and will be more susceptible to electrostatic discharge (ESD) damage. Therefore, an effective ESD protection design has become an important and indispensable part.
However, a conventional CMOS IC includes high voltage and low voltage components, and an ESD protection circuit capable of withstanding a high voltage must be designed at the high voltage I/O pin to enhance the electrostatic discharge tolerance.
For analog I/O, an ESD protection circuit has two purposes. The first purpose is to provide an electrostatic discharge path between HVDD and HVSS. The second purpose is to provide an electrostatic discharge path between analog I/O and HVSS. In the design architecture of a conventional ESD protection circuit as shown in FIGS. 5 and 6, high voltage PMOS and NMOS components are connected to create large size gate-grounded N-type NMOS (Gate-Grounded NMOS, GGNMOS) and gate-to-power P-type PMOS (Gate-VDD PMOS, GDPMOS), and the layout rule design pitch of the MOS manufacturing process is increased for ESD protection elements, These ESD protection elements are tested using a transmission line pulse (TLP) system to simulate what happens when an electrostatic discharge occurs.
As shown in FIG. 7, the typical ESD protection device's TLP curve yields a critical point at A (Vt1, It1) for the trigger voltage. As the ESD high-energy current pulse comes in, the voltage rises continuously (from 0 to A) and once it crosses the Vt1 critical point, the protection element forms a low-impedance path to discharge the ESD discharge energy so that the protection element's profile goes into the snapback area (from A to B), creating a holding voltage point B at (Vh, Ih). When the discharge energy of the ESD momentarily enters the protection element again, it also makes the characteristic curve of the protection element form a low impedance discharge circuit to discharge the energy (from B to C). If the voltage continues to rise, the vent current will be greater than the failure current (It2) to make the protection element unbearable, thus, it will enter the second breakdown region (the area above C) to burn the protection element.
Furthermore, the trigger voltage is used to record the instantaneous trigger point of the protection element entering the snapback region. The trigger voltage of the ESD protection element must be lower than the breakdown voltage (BV) of the internal circuit (Core) to enable the ESD element before the internal circuit has not been damaged by electrostatic bombardment. The holding voltage is the lowest voltage after the device enters the snapback state. This value must be higher than the operating voltage (VDD) of the circuit system to prevent the occurrence of the latch-up effect. The characteristic curves obtained from TLP measurements can help to design ESD protection devices with high ESD protection capability.
In general practical application, the first is to connect low-voltage PMOS and NMOS components in creating GDPMOS and GGNMOS for use as ESD protection components in low voltage environments; the second is to connect high-voltage PMOS and NMOS components in creating GDPMOS and GGNMOS for use as ESD protection components in low voltage environments. For low-voltage components used in low-voltage environments, the electrostatic discharge design window is relatively wide and safe since the breakdown voltage of low-voltage components is mostly about 2 times the operating voltage (for example, 3.3V devices have a breakdown voltage of 6.2V). However, for high-voltage components used in high-voltage environments, because of process constraints, the breakdown voltage of high voltage components are mostly only 1.1 to 1.5 times higher than the operating voltage (for example, the collapse voltage of 32V components is 45V), so ESD design window is relatively narrow.
If to protect the internal circuit not to enter the breakdown voltage region, the ESD protection components can cross into the latch region to damage or burn the components when suddenly entered the snapback breakdown; and vice versa.
As shown in Table 1 below, the sensitivity classification of the industrial test conducted by ESD is based on the Human-Body Mode (HBM) or the Machine Mode (MM) to simulate ESD events, in which, the sensitivity is usually classified according to the withstand voltage, and the MIL-STD-883 standard specification is adopted in the industrial test standard of the component level, and the electrostatic gun is directly struck on the IC components.
In the simulated human discharge mode basic circuit (as shown in FIG. 9) parameters, the charge current limiting resistor (R1) connected in series to the high voltage supply source can be 1-10 MΩ, the discharge resistance (R2) connected in series to the tested device is 1500 Ω, the storage capacitor (C) is 100 pF; in the industrial test standards of system level, IEC 61000-4-2 standard is adopted to to introduce electrical charges to the IC system components using an electrostatic gun. The defined simulated human discharge mode is similar to MIL-STD-883 standard specifications with the exception that the storage capacitor value and the discharge resistance value are different, such as the discharge resistance 50-100 MΩ, storage capacitor 150 pF, and the discharge energy and the electrostatic peak current are also very different. Non-standard test (copy the actual burnout experiment) is to electrically conduct the system product of IC components, and then to directly introduce static electricity to the system product of IC components according to IEC 61000-4-2 standard specifications. The system-level electrostatic gun energy is much higher than the component-level electrostatic gun energy.
TABLE 1Industry standard test sensitivity classification forhuman discharge modeClassificationSensitivityClass 10 to 1,999VoltsClass 22,000 to 3,999VoltsClass 34,000 to 15,999Volts
Test Standard: MIL-STD-883
Further, the conventional electrostatic discharge protection circuit architecture described above, even though passes the component-level standard testing of ESD industrial test, but due to the high-voltage environment is complex, a considerable proportion of the actual electricity use (which can be used by system-level industry standard test to copy the actual burnout experiment) is affected by serious electrostatic impact, leading to that the ESD protection components cross into the latch region to cause damage or burnout when suddenly entered the snapback breakdown. To explore the reason, if a TLP measurement of an ESD protection element made of high-voltage PMOS and NMOS devices shown in FIGS. 5 and 6 is conducted, it will yield a characteristic curve as shown in FIG. 10. From this curve, it can be seen that the Vt1 critical point is very close to the breakdown voltage of 43V, while Vh is much lower than the operating voltage of 32V, which is the physical characteristics of high-voltage components. Therefore, although this protection component can pass the ESD industrial test standards, when the actual power is used, the ESD protection components cross into the latch region cause damage or burnout when suddenly entered the snapback breakdown due to more serious static electricity or unstable high voltage power supply. Therefore, how to design ESD protection devices with a small area and high ESD tolerance is the subject for those in the industry to study.